1. Field of the Invention
The present invention is directed to methods and apparatus for transferring control between clock domains and, more particularly, to a method and apparatus for enabling the transfer of control between a free running system clock and a burst, source-synchronous, data clock.
2. Description of the Background
Microprocessor have made substantial advances in terms of speed of operation and the number of instructions that can be performed per second. In fact, the speed of operation of microprocessors is outpacing the speed of operation of memory devices such that it is necessary to have many memory devices responsive to a single processor in an effort to ensure that instructions and data are provided to the processor at a speed as close to the operating speed of the processor as possible.
To address the need for faster devices, a group of devices can be placed on a common bus. In such a configuration, each device operates in a coordinated manner with other devices on the bus to share data which is transmitted at a high speed. An example of such a high speed data system is described in U.S. Pat. No. 5,917,760 to Millar. Millar describes a high speed data system using a common bus and a memory sub-system commonly known as SyncLink Dynamic Random Access Memory (SLDRAM). By providing an appropriate number of memory devices and an efficient control system as used in SLDRAM, very high speed data transmissions can be achieved. However, faster systems, such as SLDRAM, are now reaching transfer speeds where memory devices cannot process the data as fast as the common bus can supply it. More specifically, as data storage address commands arrive at a memory system, it the corresponding data has not yet arrived, the address commands must be stored in a data pipeline until the data arrives. This address command backlog prevents use of the data pipeline by other processes, including transmitting other data, until the data corresponding to the address command arrives. That inconsistency in arrival times for address commands and data can result in increased data errors and lost data, but most often slows the system by creating a bottleneck of address commands.
In a source synchronous memory system, a burst data clock is set coincident with data to provide a well-timed latching clock at the receiving end of a data bus. If data capture latency is high for write data, but command bus band width is also high, it may become necessary to store several write commands and addresses before the data associated with those commands and addresses is captured. A second problem associated with a source synchronous system using a burst data clock is that the burst clock only cycles for the time the data is being sent across the bus. That has implications for completing a write command using synchronous logic because the clock that is timed for the data is only present on the bus for data capture and becomes unavailable for bother logic operations. That situation is outlined in the timing diagram of FIG. 1. As seen from FIG. 1, a write command is taken from the command bus in response to a continuous, free-running, system clock. After some period of delay, labeled the latency period in FIG. 1, data can be taken off the data bus in response to a burst data clock. A problem arises as a result of the need to resynchronize the capture clock back to the free-running system clock so that the synchronous logic can complete the write operation through the control of the data path. FIG. 1 also illustrates the preamble of the burst clock, which comprises three low clock ticks before the first pulse of the clock signal, a receive enable signal {overscore (Ren)} which transitions during the preamble, and the internal burst data clock
U.S. Pat. No. 5,895,482 is entitled Data Transfer System For Transferring Data In Synchronization With System Clock and Synchronous Semi-Conductor Memory Disclosed therein is a data transfer system having a data transfer path divided into a number of pipeline stages. A control section controls the number of pipeline stages that are activated. U.S. Pat. No. 5,844,859 is entitled Synchronous Semi-Conductor Memory Device Reliably Fetching External Signal In Synchronization With Clock Signal Periodically Supplied From the Exterior. Disclosed therein is a method by which operating frequency is increased and CAS latency is set longer, and a data write end time is delayed by a specific time in response to the change in the CAS latency. By appropriate control of the time periods, a write period for second-bit data is ensured in an SDRAM even if the operation frequency is increased.
Despite attempts to solve the aforementioned problems, the need still exists for an apparatus and method for reliably capturing command and address information with a continuous clock, capturing data at a later time with a burst clock, and coordinating the execution of the command on the later received data with the continuous clock.
The present invention is directed to an apparatus for coordinating the execution of commands with the receipt of data in response to a burst clock. Command capture logic receives command information in response to a system clock. A storage element is responsive to the command capture logic for storing certain command information such as write commands. A two stage pipeline receives the command information from the storage element in response to the burst clock and outputs the command information in response to the system clock.
The storage element may be implemented by a first in first out buffer (FIFO) responsive to both command and address information for storing the incoming write commands and associated address information. The two stage pipeline may include two delay elements, such as latches, controlled by two state counters. One state counter is clocked by the burst clock while the second state counter is clocked by the continuous clock. The data clock counter output is decoded to generate three control signals: a first signal for controlling the read side of the FIFO, a second signal for controlling the first stage of the pipeline, and a third signal to start the counter responsive to the continuous clock. The output of the counter responsive to the continuous clock is decoded and a control signal is generated to control the second stage of the pipeline and to initiate the generation of control signals to control the data path logic for executing the write command.
The method of the present invention is comprised of the steps of storing information, inputting the stored information into a pipeline in response to a burst clock, and outputting the information from the pipeline in response to a continuous clock.
The apparatus and method of the present invention accomplish the task of capturing and storing commands, such as write commands, and controlling the operation of the data path so that the write command can be executed at a later time after the corresponding data has arrived. The apparatus and method of the present invention also enable control to be shifted between the two clock domains. More specifically, control initially is with the continuous clock which is used to receive the write command and address information. Control is then transferred to the burst clock to enable the data to be received. Finally, control is transferred back to the continuous clock to enable the write command to be executed on the associated address using the later received data.
Those, and other advantages and benefits, will be apparent from the Description of the Preferred Embodiment appearing hereinbelow.